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Architectural Foundations of the HIP Ecosystem
AI022 Lesson 3
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The HIP Ecosystem is architected as a thin abstraction layer designed for source-code compatibility between AMD and NVIDIA architectures. It leverages the ROCm (Radeon Open Compute) stack, specifically utilizing the Heterogeneous System Architecture (HSA) runtime and the Kernel Fusion Driver (KFD).

1. Initialization Bootstrap

Initialization begins with low-level kernel driver handshakes via hsa_init(0, ...) and hsaKmtOpenKFD(...). These establishment calls create the communication bridge between user-space applications and AMD GPU hardware.

2. Topology & Property Discovery

Before launching kernels, the runtime identifies hardware capabilities using hsaKmtAcquireSystemProperties and hsaKmtGetNodeProperties. It maps physical memory to GPU nodes using hsaKmtMapMemoryToGPUNodes, ensuring page-table visibility for the device.

3. The Compilation Pipeline

The bridge between CUDA and HIP is built on two pillars: hipify-perl (regex-based transpiler) and hipcc (compiler wrapper).

# Porting Workflow Example
hipify-perl square.cu > square.cpp
hipcc square.cpp -o square.out

4. Versioning Logic

Compatibility is enforced via a precise formula to ensure hipRuntimeGetVersion aligns with HSA extension tables:

$$\text{HIP\_VERSION} = \text{MAJOR} \times 10^7 + \text{MINOR} \times 10^5 + \text{PATCH}$$

Application Layer (./square.out)HIP Layer (hipcc / Runtime API)HSA Runtime / Extension TablesKernel Driver (KFD) & Hardware
main.py
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